1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices and manufacturing apparatus therefor, and more particularly to a method for forming a gate oxide layer in MOS devices and other oxide layers and manufacturing apparatus therefor.
2. Description of the Related Prior Art
Manufacture of semiconductor devices and particularly MOS devices includes a number of steps of forming gate oxide layers and other oxide layers. With the recent trend toward miniaturization and very large scale integration, multi-layer poly-silicon layers have been in wide use. For instance, in 1 M-bit dynamic RAMs, a cell plate forming a part of a cell capacitor is made of a poly-silicon layer containing a high concentration of a conductive dopant. Moreover, gate electrodes of selector transistors and peripheral transistors are also made of poly-silicon layers having a high concentration of a conductive dopant.
Such poly-silicon layers having a high concentration of a conductive dopant are indispensable to today's LSI devices as wiring material and electrode material of MOS transistors. Those poly-silicon layers are grown by the CVD technique. Therefore, the poly-silicon layers are grown not only on a top surface of a semiconductor substrate but also on a back surface thereof. Because those poly-silicon layers contain a very high concentration of the conductive impurity, the poly-silicon layers may be considered as a diffusion source of the impurity on the semiconductor substrate carrying the poly-silicon layers thereon. Especially, when a surface of the semiconductor substrate is exposed in the vicinity of the poly-silicon layers containing the conductive impurity, the impurity in the poly-silicon layers may travel and move into the substrate by way of the exposed surface of the semiconductor substrate after an oxide layer is disposed on the surface of the semiconductor substrate or thermal treatment including annealing is carried out subsequent to the formation of the poly-silicon layers.
FIGS. 15(a) to 15(d) are device profiles showing the sequence of formation of a gate oxide layer of transistors in DRAMs. The device illustrated includes a P type silicon substrate 1, an isolation region 2, a cell plate 3 of N.sup.+ type poly-silicon, a capacitor insulator layer 4, a N.sup.+ type diffusion layer 5, a P type diffusion layer 6, unintentional diffusion 7 of phosphorus from the N.sup.+ poly-silicon layer, a gate oxide layer 8, an N type diffusion region 9 and an N.sup.+ type poly-silicon layer 10.
As is seen from FIGS. 15(b) and 15(c) showing the sequence of the formation of the gate oxide layer, the cell plate 3 is made of a poly-silicon layer containing a high concentration of the conductive impurity. Subsequent to the formation of the poly-silicon layer, phosphorus would externally or unintentionally enter and thermally diffuse into an adjoining transistor region exposed via a surface of the substrate during the initial stage of the formation of the gate oxide layer 8, including insertion of silicon substrates, temperature ramping and annealing. In general, the threshold voltage of MOS transistors is sensitive to and varies with chance in the impurity concentration at the surface of the substrate beneath the gate electrode. To this end, substantial variation in the threshold voltage is observed. In the case of an N channel transistor as shown in FIGS. 15(a) to 15(c), phosphorus or N type dopant diffuses itself from the cell plate 3, turning the conductivity type of the channel region of an adjoining MOS transistor into N type. The threshold voltage of that MOS transistor shifts substantially to the negative direction to render the transistor conductive at all times.
FIGS. 16(a) to 16(c) are device profiles of a LDD structure MOS transistor. The MOS transistor illustrated includes a P type silicon substrate 21, a P type well region 22, an N type well region 23, an isolation region 24, gate oxide layers 25, a P channel gate 26 of N.sup.+ type poly-silicon, an N channel gate 27 of N.sup.+ type poly-silicon, a photoresist 28, LDD phosphorus implantation 29, phosphorus-implanted LDD regions 30, N type diffusion regions 31 by self-diffusion, external diffusion of phosphorus 32 from the gate electrodes, channel regions 33, N.sup.+ type source/drain regions 34 and P type source/drain regions 35.
The transistor gates are usually formed of the poly-silicon layer 27 containing a conductive impurity. After the gate electrodes are formed, low density impurity implantation is effected on the source/drain regions by the ion implantation method to build a LDD structure therein (FIG. 16(a)). Thermal treatment is thereafter usually carried out to activate the ion implanted impurity. Under the circumstance, the impurity in the poly-silicon gate layer 27 may diffuse into the source/drain LDD region (FIG. 16(b)). Where the conductivity of the LDD region is the same as that of the impurity in the poly-silicon layer 27, the impurity concentration of the LDD region of the transistor becomes higher and eventually the transistor exhibits a short channel. In other words, in the N channel transistor of FIG. 16(c), the N type impurity concentration of the LDD region becomes higher and the diffusion length in a lateral direction becomes longer due to phosphorus atoms self-diffused from the N type poly-silicon layer 27. For this reason, the channel region 33 becomes shorter, resulting in the short channel. On the other hand, where the conductivity of the LDD region is opposite that of the impurity of the poly-silicon gate layer, the impurity in the LDD region is compensated and lowered by the impurity emerged from the poly-silicon layer. The LDD region exhibits increase in resistance and, in the worst case, renders the transistor an offset channel type transistor and eventually deteriorates drive performance.
In FIG. 16(b), phosphorus of the opposite conductivity type to the P type source/drain region of the P channel transistor diffuses itself into the source/drain region, causing compensation between the P type and N type impurities. In FIG. 16(c), a high resistance N type diffusion layer 31 is developed in the source/drain region of the P channel transistor. At this moment the P channel transistor turns to the offset channel transistor so that the threshold voltage substantially shifts to the positive direction and the drive performance of the P channel transistor remarkably drops.
FIGS. 17(a) to 17(c) are device profiles of a MOS transistor with a DDD (Double-Diffused Drain) structure. The MOS transistor illustrated includes a P type silicon substrate 41, a P type well region 42, an N type well region 43, an isolation region 44, gate oxide layers 45, a P channel gate 46 of N.sup.+ type poly-silicon, an N channel gate 47 of N.sup.+ type poly-silicon, a photoresist 48, DDD phosphorus implantation 49, phosphorus-implanted DDD regions 50, N type diffusion regions 51 by self-diffusion, external diffusion of phosphorus 52 from the gate electrodes, channel regions 53, N.sup.+ type source/drain regions 54 and P type source/drain regions 55.
Like the LDD structure device, a low concentration of an impurity is ion implanted in the DDD region (FIG. 17(a)). Thereafter, the impurity diffuse into the DDD region due to self diffusion of the poly-silicon layer or gate electrode 47 having a high concentration of an impurity during the initial stage of thermal treatment for buildup of the DDD region. When the impurity in the DDD region is of the same conductivity type as that in the poly-silicon layer gate, the short channel state is observed. If the case is reverse, the offset channel state is seen. Otherwise, if a poly-silicon layer having a high concentration of impurity is disposed on the back of the silicon substrate, the impurity may diffuse into the top surface of another silicon substrate facing against the back of the first silicon substrate in an oxidation furnace, causing the above discussed problems. The phenomenon is merely that where the poly-silicon layer containing a high concentration of a conductive impurity serves as a diffusion source to allow the impurity to diffuse into an exposed portion of a surface of the semiconductor substrate adjacent to the diffusion source. This phenomenon is called "autodoping." The extent of the autodoping greatly depends upon the temperature, time and atmosphere of thermal treatment in a thermal treatment furnace, the pitch of silicon substrate placement, the structure of a silicon substrate boat, gas flows in the furnace and the structure of an electric furnace. With a smaller pitch of silicon substrate placement, and with a closed structure of the boat, the autodoping becomes significant. Recently, vertical type electric furnaces have attracted more attention and been replacing gradually the conventional horizontal furnace. However, where the vertical type furnace is used, the autodoping is more often significantly observed.
The conventional thermal treatment furnace for carrying out annealing and oxidation is depicted in FIG. 18. The vertical type furnace is illustrated, which comprises a process tube 60, an exhaust air outlet 61, a silicon substrate 62, a boat 63, a heater 64, a cap 65, a seal 66, a pedestal 67, a gas inlet 68, and a process gas flow 69. In the conventional furnace structure, a process gas is introduced from the top of the process tube 60 and discharged from the exhaust air outlet 61 at a bottom portion of the tube after flowing inside the process tube 60. At this time the process gas flows from the top to bottom of the process tube 60. As a consequence, a layer flow is seen around the silicon substrate 62, which makes the process gas difficult to flow toward the center portion of the furnace. A gas of the conductive impurity emerging from the poly-silicon layer containing a high concentration of the impurity formed on a top surface or a back surface of silicon substrate stays between the silicon substrates around the center of the silicon substrates, because of no gas flow between the silicon substrates. As a result, the autodoping takes place at the exposed silicon surfaces of the silicon substrates. Moreover, in the impurity diffusion furnace designed to form uniformly impurity regions with the process gas, the process gas faces difficulty in flowing between the silicon substrates and among other things flowing toward the center portions of the silicon substrates. In this case, supply of the process gas toward the center portion of the silicon substrates 62 is controlled and dominated by diffusion. Where the impurity diffusion device of the above mentioned configuration is used, the impurity concentration is different from place to place within the silicon substrates 62 and lower at the center portion of the silicon substrates than at the peripheral portion thereof. In addition, a remarkable difference is observed in impurity concentration between an upper one of the silicon substrate 62 and a lower one in the process tube 60, because the density of the process gas decreases toward the bottom of the process tube 60. Where diffusion is effected with the conventional impurity diffusion furnace, the impurity concentration at the center of the silicon substrate 62 is lower than its intended value throughout the surface of the silicon substrate 62. As a result, the specific resistance thereof is high (FIG. 19). The impurity concentration is different from silicon substrate 62 to silicon substrate and among other things the impurity concentration of the silicon substrate 62 at an upper level of the process tube 60, that at an intermediate level thereof and that at a lower level thereof are different from one another. As a result, the specific resistances of the silicon substrates 62 are different.
The difference in specific resistance along the longitudinal direction of the process tube 60 varies with gas flow and exhaust air speed. In the conventional diffusion furnace, a temperature gradient is given along the longitudinal direction of the process tube 60 in an attempt to compensate for non-uniformity of the specific resistance of the silicon substrates 62. An alternative way to compensate for non-uniformity among the silicon substrates 62 is to rotate the boat 63 carrying the silicon substrates 62. However, an improvement in specific resistance can not be observed because rotation of the silicon substrates 62 itself is axis symmetric. As an improvement over the prior art devices, an injector 70 as shown in FIG. 20 is suggested along the longitudinal direction of the process tube 60. The injector 70 of FIG. 20 is designed to have apertures of a diameter of about 1 mm at an interval which is a multiple integer of the pitch of the silicon substrates placed. Within this design of the injector 70, however, the speed of a gas injected from an aperture near the gas inlet 68 is different from the gas speed at the aperture near the tip of the injector 70. The gas injection speed near the gas inlet 68 is much greater than that at the tip of the injector 70. To this end, the specific resistance is substantially different between the silicon substrates at upper and lower levels of the process tubes 60. With respect to uniformity throughout the surface of each silicon substrate 62, when the apertures are oriented toward the silicon substrate 62, the gas flow rate is too high so that a temperature drop is seen throughout the surface of the silicon substrate 62. To this end, the specific resistance increases and an appropriate value of specific resistance is not assured at a most remote portion thereof from the aperture. The silicon substrate 62 exhibits a higher value of specific resistance at the center portion thereof. The distribution of specific resistance throughout the surface of the silicon substrate 62 is suggested in FIG. 21(a). Contrarily, when the apertures are oriented to a tube wall of the process tube 60 opposite the silicon substrates 62, the gas impinges on the tube wall and decreases in speed and the gas reflected reaches the silicon substrates 62. This results in an appropriate value of specific resistance at the portion thereof near the injector 70. However, there is no sufficient speed of the gas flow and the specific resistance of the silicon substrates 62 increase at portions thereof remote from the injector 70. The distribution of specific resistance throughout the surface of the silicon substrates 62 is shown in FIG. 21(b). A silicon substrate rotation mechanism is very effective when the above mentioned injector 70 is in use. Although the rotation mechanism makes the specific resistance substantially even and uniform at the peripheral portion of the silicon substrate 62, the specific resistance is still high at the center portion of the silicon substrate 62. The distribution of specific resistance, when the injector 70 and the silicon substrate rotation mechanism are combined, is shown in FIG. 22. However, the disadvantage of the silicon substrate rotation mechanism should be noted that the mechanism is difficult to secure reliability and itself complicated and expensive, because the rotation mechanism is installed in high temperature and corrosive gas atmospheres.
Those devices may be used for impurity diffusion in some occasions and for annealing and oxidation in other occasions. When they are used for oxidation, steam generated from combustion of hydrogen gas and oxygen gas at a temperature of 760.degree. C. or higher is used for oxidant. This oxidation method is known as "pyrogenic oxidation method" and used for formation of gate oxide layers and isolation oxide layers. This method is excellent in purity and controllability of the content of the steam. The pyrogenic oxidation is generally carried out in such a manner as to eject mixed gas of oxygen and hydrogen from the tip of an injector inside a process tube of an oxidation furnace and fire the mixed gas at high temperature furnace atmosphere to generate the water vapor. At this time the ratio of the flow rate of hydrogen to that of oxygen is set at less than 180% in view of critical explosive condition and safety requirement. The temperature of the tip of the injector should be 760.degree. C. or more. The ratio of the steam to the whole oxidizing atmosphere is determined by adjustment of the flow rate of oxygen to hydrogen. The rate of growth of an oxide layer during steam oxidation process is determined by the partial pressure of steam in the atmosphere. In other words, the partial pressure of steam in the oxidizing atmosphere may be lowered when the gate oxide layer should be thin and thickness controllability is of importance. The steam may be generated through combustion of hydrogen and oxygen in an oxygen rich atmosphere.
In those conventional pyrogenic oxidation methods, combustion occurs within the process tube. However, if combustion of hydrogen and oxygen occurs within the process tube, the thickness variation problems come up because the temperature in the process tube become unstable due to high temperature combustion gases. To this end, the external combustion method is often used where a combustion chamber is placed outside the process tube and an exclusive combustion heater is used to fire hydrogen and oxygen by a combustion heater. FIG. 23 is a conceptional diagram of a conventional oxide layer formation furnace with a combustion heater installed outside the process tube. The oxide film formation furnace illustrated includes a process tube 81, a silicon substrate 82, a boat 83, an external combustion chamber 86, an external combustion heater 87, an injector 88, an oxygen port 89, a hydrogen port 90, and a hydrooxygen flame 91. Hydrogen gas from the hydrogen port 90 and oxygen gas from the oxygen port 89 are mixed and heated by the external combustion heater 87 in the injector 88. The hydrogen and oxygen gas heated up to higher than 760.degree. C. fires and then is sent to the combustion chamber 86 as the hydrooxygen flame 91 and the steam generated is conveyed to the process tube 81.
In the manufacture of the semiconductor devices, the autodoping causes the crucial problems as discussed above, including substantial change in the threshold voltage of the MOS transistors, the short channel or offset gate in the MOS transistors, increase in the resistance of the contact diffusion layers and increase in the diffusion depth of the junctions.
In spite of the above discussed problems, the IC technology has advanced to VLSI and the multi-layer poly-silicon layers have been widely used as gate electrodes in the industry. Thus, those problems caused by the autodoping tend to have become serious. In particular, the conventional horizontal type electric furnaces have been replaced by the vertical electric furnaces due to the requirement of uniform thickness of oxide layers and ease of automation and other factors. The inventors' investigation has revealed that the vertical type electric furnace tends to cause the autodoping more easily than the horizontal type, because gases are not equally distributed between the adjacent silicon substrates and especially at the center portion of the silicon substrates due to the structural attributes of the vertical type. In the case where the poly-silicon layers containing the conductive impurity are disposed on the back and front surfaces of the silicon substrates, selective removal of the backside poly-silicon layers prevents the potential autodoping during subsequent thermal processing. However, where the poly-silicon layers are present as desired patterning on the top surface of the silicon substrate, the problems of autodoping remains pending and unresolved.
In the conventional thermal treatment devices, there is a demand for a structure by which impurity-containing gases are supplied uniformly throughout the silicon substrates and also in the longitudinal direction of the process tube 60 without a silicon substrate rotation mechanism.
There are several ways to make equal the gas ejection speed from the gas orifices 71 arranged along the longitudinal direction of the injector 70. One way is to gradually increase the diameter of the gas ejection orifices 71 from the gas inlet 68 of the injector 70 to the tip of the injector 70. Another way is to decrease the spacing of the gas orifices 71. Those methods, however, face difficulty in calculating the diameter of the gas outlets 71 in order to attain equal speed and machining the gas outlets 71. Due to the aging, the diameter of the gas orifices 71 would change and the respective gas orifices would lose balancing. Another attempt to secure uniformity throughout the surface of the silicon substrate is to use more than one injector 70. However, this approach needs two or more gas systems and balancing among the injectors 70. This makes a spacial margin (or clearance) smaller between the process tube 60 and the silicon substrates 62.
In the conventional pyrogenic oxidation method and particularly the pyrogenic oxidation in oxygen-rich atmosphere, normal combustion condition is not seen for combustion of hydrogen and oxygen gases at the tip of the injector 88, because of a much amount of oxygen gas. Normal combustion is attained when the ratio of the hydrogen flow to oxygen flow is in the neighborhood of 180%, where the temperature of the hydrooxygen flame 91 is relatively low. However, in the event that oxygen content is greater, combustion is explosive and the temperature of the hydrooxygen flame 91 is extremely high due to an excessive amount of oxygen. In the conventional design of injector 88, the hydrogen and oxygen gases are mixed and ejected from the single injector 88. Because the tip of the injector 88 is usually narrowed in diameter, the ejection speed of the hydrogen/oxygen mixed gas from the tip of the injector 88 is extremely high.